- Available as CXP to XGMII (device) or XGMII to CXP (host) Bridge IP Cores
- Compatible with Xilinx 7 Series (and newer), Intel Cyclone/Arria 10 and Microchip PolarFire devices
- Compatible with S2I and third-party CoaXPress IP Cores
- Delivered with a working reference design (when purchased with the CoaXPress IP Core)
The CoaXPress-over-Fiber Bridge IP Core allows to connect a CoaXPress IP Core to an XGMII (10 Gbps Media Independent Interface) bus inside an FPGA. XGMII, as defined in IEEE Std 802.3 Clause 46, is the main access to the 10G Ethernet physical layer. The generic nature of this interface facilitates mapping the CoaXPress signaling into the PCS/PMA Ethernet sublayers.S2I's CoaXPress-over-Fiber Bridge IP Core is available as a device or host version. In a camera (device), it converts CoaXPress packets to XGMII packets going towards an Ethernet PCS/PMA block. In a frame grabber (host), it converts XGMII packets to CoaXPress packets.
